A computer processor typically performs read and write operations to both memory and input/output devices on a frequent basis. A write operation usually involves transmitting the data to be written along with the address of the location being written to. Conversely, with a read operation, after the read command has been issued, the processor and the bus can sit idle while waiting for the response to the read command to be forthcoming. Although the processor may be allocated to another task in the meantime, the bus can be stuck sitting idle unable to transmit another command (transmit other data) until the read command is responded to thus allowing the bus to accept another command. If the device being read is relatively fast, then the delay may only be for a short time and the performance degradation may be acceptable. However, if the device being read is relatively slow, then the bus may be sitting idle for a considerable, and unacceptable, period of time.
One prior approach to improving bus utilization on read commands is to limit the types of devices which can be read. If only a global memory may be read then, because there is no mechanical delay and because the global memory is most likely directly connected to the bus, the bus is not idle for extemely long periods of time. In this way, the bus would have a shorter average idle time. However, the bus is still idle when a read command is outstanding and other read commands can not be issued during this idle period.
Another prior approach to improving bus utilization on read commands is to improve the speed of the bus itself. In this way, when the read response is ready, it will be transmitted that much faster and thus free up the bus that much sooner. Additionally, this would decrease the time the requesting processor waits for a read response as both the read command and the read response would be transmitted more quickly. However, merely improving the bus speed does nothing to eliminate the idle time the bus experiences while it is waiting for a read response. Thus, additional read commands would still have to wait for responses to earlier read commands to be completed before these additional read commands could be issued.